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Sunitha M S

Associate Professor
  • Teaching

About

Obtained her B.Sc degree from Bangalore University and Secured University 8th Rank Obtained her M.Sc (Physics) degree from Bangalore University and Secured University 2nd Rank Obtained her M.S (By Research) degree from VIT University, Chennai Campus. She was the first research student in the school of Electronics Engineering, SENSE, to obtain a research degree from this campus. The area of research being Memory Design and Testing. She has also completed a Proficience course on Embedded System Design from IISc, Bangalore. She has a total teaching experience of 32 years with 22 years at PESIT/PES University. She has taught a variety of subjects at both UG and PG level. She has authored more than 15 papers in International Journals and Conferences. Her current interest is in Analog circuits and Memory Designing.

Education

  • M.S (By Research), VIT University

Experience

  • Associate Professor, PES University, 2000 - Till date

  • Lecturer, NMKRV College for Women, June 1990 - Oct 2000

Achievements

  • Secured University 2nd Rank in M.Sc(Physics) from Bangalore University

  • Secured University 8th Rank in B.Sc from Bangalore University

Teaching

  • Total teaching experience is 32 years. Taught a variety of subjects at both UG and PG level. She was invited to deliver guest lectures at various Institutions like Don Bosco Institute of Technology, PESIT South Campus etc. Her teaching has always been appreciated by her students which is reflected in the student feedback which has always been above 90%.

Responsibilities

  • Time-Table Officer

  • Class incharge

  • Lab Incharge

  • 8th Sem Project Co-ordinator

  • LIMS Co-ordinator

  • Test Co-ordinator

  • Faculty Advisor

  • Anchor faculty for various subjects

Research Interest

  • Obtained her M.S (By Research) degree from VIT University, Chennai Campus. Her research domain is VLSI and the topic of her thesis was " Error Detection and Correction in Memory".

  • Currently she is pursuing her Ph.D in the area of Analog VLSI. She has guided many student projects, a majority of which have been converted to conference papers.

Conferences

  • D. Sahoo, A. Deshpande and M. Sunitha, "Study of Different Adders Using Full Swing Gate Diffusion Input," 2020 5th IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE), 2020, pp. 1-4

  • P Rao, P Babshet, RA Babu, MS Sunita, "Encoder and Adaptive Decoder for a (15, 6, 2) DEC-TED BCH Code", 2020 IEEE 17th India Council International Conference (INDICON)

  • Pradeep, K; Mohith, B; Manjunath, KP; Sunita, MS, "Comparative analysis of FinFET and Planar MOSFET SRAMs", 2020 International SoC Design Conference (ISOCC), pp- 11-12.

  • Sunita, MS; Mayur, GD; Bedi, Preet; Verma, Nagesh; Tantry, Shashidhar, "50 MHz 3-Level Buck Converter with added Boost Converter", 2020 International SoC Design Conference (ISOCC), pp. 109- 110.

  • Vasudev, Prerana; Nerlige, Tanmayee M; Akhil Siddarth, Sunita, MS, "Analysis of MTJ Based Ternary Content Addressable Memory With and Without Match-Line Pre-Charge", 2020 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)

  • Sanjana V Manturshettar, MS Sunita, "A low noise low power Operational Transconducatance Amplifier for biomedical applications", 2019 IEEE 16th India Council International Conference (INDICON)

  • MS Sunita, BS Rakshitha, K Sankirthana, Shashidhar Tantry, "A high efficiency, fast response Buck converter for low voltage applications", 2019 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)

  • Sharath Rao, KS Shashikanth, Ranjith Srinivas, MS Sunita"Magnetic RAM based filter design for low power signal processing in IOT applications", 2017 14th IEEE India Council International Conference (INDICON)

  • Smaran Adarsh, Tanmay M, Sunita M S, "Single-Ended Sub-threshold 9T SRAM Cell With Ground Cut-Off", CSTIC 2019

  • Sunita, M.S., Kanchana Bhaaskaran, Deepakakumara Hegde and Pavan Dhareshwar (2013). Error Detection and Correction in Embedded Memories using Cyclic Codes, Proc. of the Int. Conf. on VLSI, Communication, Advanced devices, Signals & Systems and Networking, (VCASAN), Lecture Notes in Electrical Engineering, Springer India, Vol. 258, Chap. 16, pp. 109-116.

  • Sunita. M S, D. Abhinand R B, L. K. Shetty and S. Tantry, "Analysis of Switched Capacitor Buck Converter using Sampling Frequency Control Method," 2021 IEEE 8th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON), 2021, pp. 1-4, doi: 10.1109/UPCON52273.2021.9667565

  • P. Vasudev, S. S. Murthy and S. M. S, "A Novel Error Correction Code with Reduced Memory Utilization and Increased Accuracy," 2021 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), 2021, pp. 1-6, doi: 10.1109/CONECCT52877.2021.9622657.

  • B. N. Tejas, K. S. Kumar and S. M. Sunita, "Multiple Bit Error Correction Codes for Memories in Satellites," 2022 IEEE 7th International conference for Convergence in Technology (I2CT), 2022, pp. 1-6, doi: 10.1109/I2CT54291.2022.9824813.

  • Sunita. M. S, T. Somashekhar and S. Tantry, "Adaptive ON - Time Boost Converter in 45nm for Solar Cell Applications," 2021 18th International SoC Design Conference (ISOCC), 2021, pp. 135-136, doi: 10.1109/ISOCC53507.2021.9613879.

Journals

  • Sunita, M.S., V.Chiranth, H.C. Akash and Kanchana Bhaaskaran V.S (2015). Pipeline Architecture for fast decoding of BCH Codes for NOR Flash Memory, ARPN Journal of Engineering and Applied Sciences, Vol. 10, No. 8, pp. 3397-3404.

  • Sunita, M.S and Kanchana Bhaaskaran V.S (2013). Matrix Code based multiple error correction technique for n-bit memory data, Int. Journal of VLSI Design and Communication Systems (VLSICS), Vol. 4, No.1, pp 29-37.

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