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Electronics & Communications
RingRoadCampus
sunitha@pes.edu
+91-80-26721983 Extn 764

Sunitha M S

Associate Professor
Bio
Teaching
Responsibilities
Research
Publications

Obtained her B.Sc degree from Bangalore University and Secured University 8th Rank Obtained her M.Sc (Physics) degree from Bangalore University and Secured University 2nd Rank Obtained her M.S (By Research) degree from VIT University, Chennai Campus. She was the first research student in the school of Electronics Engineering, SENSE, to obtain a research degree from this campus. The area of research being Memory Design and Testing. She has also completed a Proficience course on Embedded System Design from IISc, Bangalore. She has a total teaching experience of 29 years with 19 years at PESIT/PES University. She has taught a variety of subjects at both UG and PG level. Her current interest is in the VLSI domain.

Education

  • M.S (By Research), VIT University

Experience

  • Associate Professor, PES University, 2000-Till date

Achivements

  • Secured University 2nd Rank in M.Sc(Physics)
  • Secured University 8th Rank in B.Sc
  • Total teaching experience is 29 years. Taught a variety of subjects at both UG and PG level. She was invited to deliver guest lectures at various Institutions like Don Bosco Institute of Technology, PESIT South Campus etc. Her teaching has always been appreciated by her students which is reflected in the student feedback which has always been above 90%.
  • Time-Table Officer
  • Class incharge
  • Lab Incharge
  • 8th Sem Project Co-ordinator
  • LIMS Co-ordinator
  • Test Co-ordinator
  • Faculty Advisor
  • Anchor faculty for various subjects

Research Interest

  • Obtained her M.S (By Research) degree from VIT University, Chennai Campus. Her research domain is VLSI and the topic of her thesis was " Error Detection and Correction in Memory".
  • Currently she is pursuing her Ph.D in the area of Analog VLSI. She has guided many student projects, a few of which are have been converted to conference papers.

Conferences

  • D. Sahoo, A. Deshpande and M. Sunitha, "Study of Different Adders Using Full Swing Gate Diffusion Input," 2020 5th IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE), 2020, pp. 1-4
  • P Rao, P Babshet, RA Babu, MS Sunita, "Encoder and Adaptive Decoder for a (15, 6, 2) DEC-TED BCH Code", 2020 IEEE 17th India Council International Conference (INDICON)
  • Pradeep, K; Mohith, B; Manjunath, KP; Sunita, MS, "Comparative analysis of FinFET and Planar MOSFET SRAMs", 2020 International SoC Design Conference (ISOCC), pp- 11-12.
  • Sunita, MS; Mayur, GD; Bedi, Preet; Verma, Nagesh; Tantry, Shashidhar, "50 MHz 3-Level Buck Converter with added Boost Converter", 2020 International SoC Design Conference (ISOCC), pp. 109- 110.
  • Vasudev, Prerana; Nerlige, Tanmayee M; Akhil Siddarth, Sunita, MS, "Analysis of MTJ Based Ternary Content Addressable Memory With and Without Match-Line Pre-Charge", 2020 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)
  • Sanjana V Manturshettar, MS Sunita, "A low noise low power Operational Transconducatance Amplifier for biomedical applications", 2019 IEEE 16th India Council International Conference (INDICON)
  • MS Sunita, BS Rakshitha, K Sankirthana, Shashidhar Tantry, "A high efficiency, fast response Buck converter for low voltage applications", 2019 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)
  • Sharath Rao, KS Shashikanth, Ranjith Srinivas, MS Sunita"Magnetic RAM based filter design for low power signal processing in IOT applications", 2017 14th IEEE India Council International Conference (INDICON)
  • Smaran Adarsh, Tanmay M, Sunita M S, "Single-Ended Sub-threshold 9T SRAM Cell With Ground Cut-Off", CSTIC 2019
  • Sunita, M.S., Kanchana Bhaaskaran, Deepakakumara Hegde and Pavan Dhareshwar (2013). Error Detection and Correction in Embedded Memories using Cyclic Codes, Proc. of the Int. Conf. on VLSI, Communication, Advanced devices, Signals & Systems and Networking, (VCASAN), Lecture Notes in Electrical Engineering, Springer India, Vol. 258, Chap. 16, pp. 109-116.

Journals

  • Sunita, M.S., V.Chiranth, H.C. Akash and Kanchana Bhaaskaran V.S (2015). Pipeline Architecture for fast decoding of BCH Codes for NOR Flash Memory, ARPN Journal of Engineering and Applied Sciences, Vol. 10, No. 8, pp. 3397-3404.
  • Sunita, M.S and Kanchana Bhaaskaran V.S (2013). Matrix Code based multiple error correction technique for n-bit memory data, Int. Journal of VLSI Design and Communication Systems (VLSICS), Vol. 4, No.1, pp 29-37.