Dr. Annapurna K Y
Associate Professor
- Teaching
About
Annapurna K Y obtained her B.E. in ECE from Bangalore University, M.Tech. in Electronics from Visvesvaraya Technological University, Belgaum and Ph.D in the area of Hardware Security from VTU, Belgaum. She has teaching experience of 14 years and Industry experience of 5 years. She is a member of IEEE . Her areas of interest are Analog and Digital VLSI.
Assistant professor, PESU, 2010 - August 2023
Associate professor, PESU, 2023 - Till date
Basic Electronics
Electronic Devices and Circuit Theory
Linear Integrated Circuits
Low Power VLSI
CMOS VLSI Design
Synthesis and Optimization of Digital Circuits
Network Analysis
Design of Analog CMOS Circuits
Design of Digital VLSI Circuits
FPGA Architectures and Applications.
Class Incharge
EWD Coordinator
Test Coordinator
Member of Exam coordination team(ECE Dept)
Class Committee Meeting Coordinator
PESU Academy coordinator
Project coordinator
Hardware security
Lightweight Cryptography
Analog and Digital VLSI
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Significance-Driven Logic Compression for Energy Efficient Multiplier Design In Asian Journal of Convergence in Technology -2020 Volume: VI Issue: II
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" Implementation of 32-Bit Complex Floating Point Multiplication using Vedic multiplier,Array multiplier,CIFM multiplier using Verilog" in INOCON 2020.
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"Numerically Controlled Oscillator (NCO) Based Frequency Converter" in IJCA - 2014
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"High Performance Reconfigurable Routers for Power Optimization " at WiSE-2013, National Conference on Wireless Communication, Signal Processing, Embedded Systems
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"FPGA Implementation of Iterative Log Multiplier Using Operand Decomposition For Image Processing Application" in IJRASET - 2014.
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"An Analysis of Stream and Block Ciphers for Scan Encryption," 2022 2nd International Conference on Power Electronics & IoT Applications in Renewable Energy and its Control (PARC), 2022, pp. 1-5, DOI: 10.1109/PARC52418.2022.9726687.
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"Dual Obfuscation Techniques for DSP Based Circuits" in 2024 IEEE 4th International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA)
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“A Lightweight Hardware Secure and Reliable Framework using Secure and Provable PUF for IoT Devices against the Machine Learning Attack” published in the International Journal of Circuits, Systems and Signal Processing Volume 16, 2022 Issue No. Art. #86, Page No. p.699-709,published by NAUN Journal.
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“Lightweight novel Dynamic Obfuscation-Based mechanism to enhance the hardware security in IoT Devices” published in the Journal Advanced Engineering Science, Volume 54, 2022 Issue No. 02, Page No. p.2239 – 2257, published by AES Journal.
Education
B.E, DSCE
M.Tech, BMSCE
Ph.D, VTU