Mahesh Awati
Associate Professor
- Teaching
About
Prof.Mahesh Awati holds M.Tech degree from VTU,Belagavi. His research interests include Digital VLSI Design, Computer Architecture and In Memory Computing. Currently he is serving as Associate Professor in Dept. of Electronics & Communication Engineering and associated with Centre for Heterogeneous and Intelligent Processing Systems (CHIPS), Electronic City campus.
Lecturer, Sandur Polytechnic, Yeshwantpur, 2001 - 2003
Lecturer, Don Bosco Institute of Technology, 2005 - 2007
Assistant Professor and Head of the Department, YDIT, Bangalore, 2007 - 2011
Assistant Professor, PESIT - Bangalore South Campus, 2011 - 2014
Associate Professor, PESIT-Bangalore South Campus, 2014 - 2019
Associate Professor, PES UNIVERSITY, Electronic City Campus, Bangalore, 2019
Conducted workshops for UG/PG students on topics in Embedded System Design and applications.
Embedded System Design Concepts - A simple approach using Embedded C and ARM Cortex M3 In this workshop, Embedded system design using protocols like CAN for Automotive automation system and application using technologies like GSM, GPS, RFID were covered.
Embedded System Design and its protocols using ARM Cortex M3 In this workshop, Embedded system design using protocols like UART, SPI, I2C for automation system and application using technologies like GSM, GPS, RFID were covered.
Played role in getting Customized Development board developed for Embedded System Labs to make them compatible with existing interfacing cards.
Digital VLSI Design
VLSI Circuits
Advanced VLSI Deign
Embedded System Design
Microcontroller MSP430
Embedded System and Microcontroller ARM Cortex M3
Microcontroller 8051
Automotive Electronics
DSP Architecture and Algorithm
Network Analysis and Synthesis
Microprocessor 8085,8086
Computer Architecture
RISC-V Architecture
M.Tech Coordinator , Class Teacher, Mentor, Syllabus Setting Member for VLSI domain (Internal), Time Table coordinator, Anchor .
Digital VLSI, Computer Architecture and In Memory Computing.
Mahesh A A, AND Raja K B ?Design of Efficient Steganography Model using Lifting based DWT and Modified LSB Method on FPGA, IJACSA, Volume 10, Issue 10, October 2019
Education
B.E, BEC Bagalkot, Karnataka University , Dharwad, 2000
M.Tech, BVB CET, Hubli, VTU Belgavi, 2005