Dr. Rashmi Seethur

Associate Professor
  • Teaching


Dr. Rashmi Seethur Completed BE in Electronics and Communication from Visveswaraya Technological University in 2004. Completed Master of Technology in VLSI and Embedded systems, 2012 with CGPA of 8.09 at UTL Technologies Limited VTU Extension Centre Bangalore. Completed Ph.D. in CMOS RF circuit design in 2019 from Visveswaraya Technological University. Her research interests are Analog circuit design, CMOS Amplifier design, RF circuit design and reversible logic. She has a teaching experience of about 15 years. She is a life member for IACSIT.


  • BE ECE, 2004

  • M.Tech VLSI and Embedded Systems, 2012

  • Ph.D RF CMOS circuit design, 2019


  • Analog circuit design

  • Digital design using Verilog

  • Low power design

  • Control systems

  • Network analysis

  • CMOS VLSI design

  • Linear integrated circuits


  • NAAC Coordinator

  • Class In Charge

  • Faculty Advisor

Research Interest

  • Analog circuit design

  • CMOS Amplifier design

  • RF circuit design and reversible logic


  • Rashmi S B, Pavan Kumar B V, Bindhu "Design Of 60 GHz CMOS Power Amplifier To Improve Power Added Efficiency" IEEE conference 2017 at GAT, Bangalore.

  • Rashmi S B, R.Sindhuja "Quantum Efficient reversible ALU" in a National conference NCIET held at Christ University Faculty of Engineering, Bangalore in Feb,2015.

  • Rashmi S B , Dr. Siva yellampalli "60GHz inductance degeneration low noise amplifier" at ICCIC 2014,IEEE at Park engineering college , Coimbatore.

  • Praveen B, Tilak B G and Rashmi S B, "A Novel High Speed Synthesized Adder/Subtractor" Third IEEE International Conference on Computer Modeling and Simulation, pp. 377 - 380, January 2011.

  • Tilak B G, Rashmi S B and Praveen B "A Novel Optimized Reversible BCD adder using reversible CL gate" Third IEEE International Conference on Computer Modeling and Simulation, pp. 377 - 380, January 2011

  • Sandeep Raghu T C and Rashmi SB "Design of low power carry look ahead adder and BCD adder using GDI technique" Third IEEE International Conference on Computer Modeling and Simulation, pp. 377 - 380, January 2011

  • Praveen B, Tilak B G and Rashmi S B "Novel High Speed Reversible adder "International conference on Demand Computing July 2011.

  • Rashmi S B Praveen B and Shreedhar HK "A novel quantum efficient ALU design"

  • Rashmi SB Praveen B and Tilak BG "Novel Optimized Reversible universal logic gates" Knowledge Utsav conducted by Jain University.


  • Rashmi S. B., Siva S. Yellampalli, H K Shreedhar "60 GHz common gate single stage current reuse cascode LNA topology for high data rate applications" Journal of Electronic Materials. October 2020. published by Springer US

  • Rashmi S. B., Siva S. Yellampalli "Design of A 60 GHz Power Amplifier in A 45nm CMOS" International Journal of Reconfigurable and Embedded Systems Vol. 8, No. 1, March 2019, Pp. 14~26 ISSN: 2089-4864, DOI: 10.11591/Ijres.V8. I1. Pp14-26. (SCOPUS INDEXED)

  • Rashmi S. B., Siva S. Yellampalli. "Design and analysis of 60GHz frequency divider using MCML logic" Grenze journal name, Volume. 1, Issue.1, May 2015.

  • S. B. Rashmi, Siva S Yellampalli "Design and Implementation of Low Noise Amplifier At 60GHz using Current Mirror Feedback" International Journal of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-8 Issue-9S3, July 2019. (SCOPUS INDEXED)

  • Rashmi S B, Dr. Siva S Yellampalli "A 60GHz High Gain CG-CG Current Reuse Low Noise Amplifier for Inter Satellite Communication for Space" International Journal of Pure and Applied Mathematics Volume 119 No. 14 2018, 95-101 ISSN: 1314-3395 (on-line version). (SCOPUS INDEXED)

  • Rashmi S.B, R. Sindhuja "Design and implementation of high speed LFSR" in International Journal of Engineering Research and General Science Volume 3, Issue 1, January-February, 2015 ISSN 2091-2730.

  • Rashmi SB Praveen B and Tilak BG "Novel optimized Reversible BCD adder/subtractor" IACSIT International Journal of Engineering and Technology vol 3 no3 June 2011 pg no 230-235

  • Shreedhar HK Rashmi SB and Umarani TG "A Novel RSU algorithm for secured communication" IJEST vol 3 no2 pg no 1222-1227 ISSN :0975-5462

  • Rashmi SB and Dr. Siva S Yellampalli "Design and Implementation of Phase frequency detector and charge pump for high frequency PLL" International Journal of Soft Computing and Engineering (IJSCE) ISSN: 2231-2307, Volume- 2 Issue-2, May 2012

  • Praveen B Rashmi SB and Tilak BG "Transistor implementation of reversible PRT gates" International Journal of Engineering Science and Technology(IJEST) vol 3 no 3 Mar 2011 ISSN:0975-5462

  • Rashmi SB and Shreedhar HK "Design of novel optimized reversible multiplier" Journal of computing vol 3 issue 3 Mar 2011 pg no 82-87 ISSN:2151-9617

  • Rashmi SB Shreedhar HK and Umarani TG "Optimized reversible Montgomery multiplier" International Journal computer science and information Technology(IJCSIT) vol 2(2), 2011,pg no 701-706 ISSN: 0975-9646

  • Rashmi SB Praveen B and Tilak BG "An Optimized design of 4-bit Reversible Magnitude comparator and binary subtractor" Elsevier 2011

 Staff Contacts
 Staff Campus Location
 RR Campus

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