Shashidhara M
Assistant Professor
- Teaching
About
Shashidhara M received his Bachelor of Engineering (B.E.) degree in Electronics and Communication Engineering and his Master of Technology (M.Tech.) in VLSI and Embedded Systems, both from Visvesvaraya Technological University (VTU). Currently, he is pursuing his Ph.D. at the National Institute of Technology (NIT), Surat. With over a decade of experience in teaching and more than three years dedicated to research, he has contributed significantly to academia. His research work has been featured in esteemed journals such as IEEE Transactions and Elsevier. Additionally, Shashidhara has successfully cleared the Graduate Aptitude Test in Engineering (GATE) in the years 2016, 2017, and 2019.
Teaching and learning, guiding UG and PG projects and Curriculum refinement
IQAC team member
Spintronics
Semiconductor Device Modelling
Novel NVM architectures
Magnetic memories
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https://scholar.google.com/citations?user=_By68p0AAAAJ&hl=en
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1. Shashidhara M, S. Srivatsava, S. Panwar, V. Nehra, R. Kamal and A. Acharya, ”Impact of Unconventional Torque on the Performance of Weyl-Semimetal-Based SOT-MTJ: A Micromagnetic Study,” in IEEE Transactions on Electron Devices, vol. 71, no. 3, pp. 2177-2183, March 2024, doi: 10.1109/TED.2024.3353707
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2. Shashidhara M., S. Srivatsava, S. Panwar and A. Acharya, ”Spin-Orbit Torque Magnetic Tunnel Junction based on 2-D Materials:Impact of Bias-Layer on Device Performance,” in Solid-State Electronics, 2023 Volume 208, 2023, https://doi.org/10.1016/j.sse.2023.108757.
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3. Shashidhara M., V. Nehra, S. Srivatsava, S. Panwar and A. Acharya, ”Investigation of Field-Free Switching of 2-D Material-Based Spin–Orbit Torque Magnetic Tunnel Junction,” in IEEE Transactions on Electron Devices, vol. 70, no. 3, pp. 1430-1435, March 2023, doi: 10.1109/TED.2023.3237654.
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4. S. Srivastava, Shashidhara M. and A. Acharya, ”Investigation of Self-Heating Effect in Tree-FETs by Interbridging Stacked Nanosheets: A Reliability Perspective,” in IEEE Transactions on Device and Materials Reliability, Dec 2022, doi: 10.1109/TDMR.2022.3227942.
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5. S. Panwar, S. Srivastava, M. Shashidhara and A. Acharya, ”Performance Evaluation of High-K Dielectric Ferro-Spacer Engineered Si/SiGe Hetero-Junction Line TFETs: A TCAD Approach,” in IEEE Transactions on Dielectrics and Electrical Insulation, vol. 30, no. 3, pp.1066-1071, June 2023, doi: 10.1109/TDEI.2023.3266413.
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6. S. Srivastava, S. M., S. Panwar, S. Yadav, A. Acharya, “Understanding the Impact of Extension Region on Stacked Nanosheet FET: Analog Design Perspective,” Solid-State Electronics, Elsevier, vol. 208, August 2023, 108758, ISSN 0038-1101, doi:10.1016/j.sse.2023.108758.
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7. S. Panwar, S. Srivastava, Shashidhara M., Deepak Joshi, Abhishek Acharya, “Performance optimization of epitaxial-layer based Si/SiGe hetero-junction area scaled tunnel FET label-free biosensors considering steric hindrance”, Solid-
Teaching
Analog Circuit
VLSI related subjects
Network Synthesis
Signals and Systems
Semiconductor Device Modelling